DMA_CRD

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Interpret as DMA_CRD

DMA Configuration Register

DATA_WIDTH	The data bus width of the AXI master interface. 3 (Val_0x3): 64-bit.
WR_CAP	Write issuing capability that programs the number of the outstanding write transactions. 3 (Val_0x3): 4 outstanding write transactions.
WR_Q_DEP	The depth of the write queue. 7 (Val_0x7): 8 lines.
RD_CAP	Read issuing capability that programs the number of the outstanding read transactions. 3 (Val_0x3): 4 outstanding read transactions.
RD_Q_DEP	The depth of the read queue. 7 (Val_0x7): 8 lines.
DATA_BUFFER_DEP	The number of the lines that the data buffer contains. 31 (Val_0x1F): 32 lines.

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